08 Jun In figure, the base and limit registers contain the same value
Question
1. In figure, the base and limit registers contain the same value, 16,384. Is this just an
accident, or are they always the same? It is just an accident, why are they the same in
this example?
2. What is the difference between a physical address and a virtual address?
3. What kind of hardware support is needed for a paged virtual memory to work?
4. Suppose that a machine has 48-bit virtual addresses and 32-bit physical addresses.
(a) If pages are 4 KB, how many entries are in the page table if it has only a single
level? Explain.
(b) Suppose this same system has a TLB (Translation Lookaside Buffer) with 32 entries.
Furthermore, suppose that a program contains instructions that fit into one
page and it sequentially reads long integer elements from an array that spans thousands
of pages. How effective will the TLB be for this case?
5. A computer with a 32-bit address uses a two-level page table. Virtual addresses are
split into a 9-bit top-level page table field, an 11-bit second-level page table field, and
an offset. How large are the pages and how many are there in the address space?
6. If FIFO page replacement is used with four page frames and eight pages, how many
page faults will occur with the reference string 0172327103 if the four frames are initially
empty? Now repeat this problem for LRU.
7. Need solution to question 33.
8. Need solution to question 36.
9. It has been observed that the number of instructions executed between page faults is directly proportional to the number of page frames allocated to a program. If the available
memory is doubled, the mean interval between page faults is also doubled. Suppose that a normal instruction takes 1 microsec, but if a page fault occurs, it takes 2001 μ sec (i.e., 2 msec) to handle the fault. If a program takes 60 sec to run, during which time it gets 15,000 page faults, how long would it take to run if twice as much memory were available?
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