15 Jun a new h.w
1) The two State Diagrams shown below interconnected to form a single state machine. That is the first state diagram provides an additional output that acts as a input control bit to the second state diagram. Both state diagrams can be used independently to develop separate state machines. However these two machines are connected by that single control bit and are drawn together as a single logic diagram.
Once the design is complete, use a present state next state table to show the entire operation of the circuit. This table may be very long.
For full credit include the circuit diagram, characteristic tables, transition tables, next state tables, K-maps and resulting equations for the design.
2) Design an 8 bit asynchronous counter using J K Flip Flops and any additional logic gates required to complete the design.
Once the counter is designed, develop a way to make the counter run slow or fast based on a single bit. Such as logic 0 has it count slow and logic 1 has it count fast. The fast count should be eight times faster than the slow count.
Draw the complete counter design including your solution for the speed control. Show the design works using a timing diagram for the counter. Show that your speed control works by using a separate timing diagram.
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