03 Jun ECET 105 Week 7 iLab Add-Subtractor using Flip-Flops NEW
I. OBJECTIVES
To test the operation of a 74LS74 D flip-flop and compare the operation with the predicted behavior
To test the operation of a 74LS112 J-K flip-flop and compare the operation with the predicted behavior
To measure propagation delays of a 74LS112 J-K flip-flop
To build and test an enhanced adder-subtractor
II. PARTS LIST
Equipment:
IBM PC or Compatible with Windows 2000 or Higher
Quartus II Design Software—Version 9.1
Frequency Generator
Oscilloscope
Parts:
2 – 330 Ω resistors, ¼ W 2 – Red LEDs
1 – 74LS74 dual D flip-flop 1 – Green LED
1 – 74LS112 dual J-K flip-flop 1 – SPDT Switch, DIP configuration
1 – eSOC III FPGA Board
III. PROCEDURE
A. Test the 74LS74 D Flip-Flop
Build the D flip-flop circuit shown in Figure 7.1. The LEDs are wired as active-LOW since the flip-flop can supply more current in a low state than in a high state. This means that the green LED is on when is HIGH and the red LED indicates Q is HIGH. Remember to attach VCC to pin 14 and ground to pin 7.
Using the circuit, verify that the operation follows the truth table for this device.
What happens when both and are set low?
Build the J-K flip-flop circuit shown in Figure 7.2. Remember to attach VCC to pin 16 and ground to pin 8.
Using the circuit, verify that the operation follows the truth table for this device.
Increase the pulse generator output to 1.0 MHz. Set the switches so that all of the flip-flop inputs are high and remove the LEDs and resistors. Using the oscilloscope, measure the propagation times for the Q output from the active clock edge. Record the value below.
Using Quartus II, modify the circuit from Lab 5 as shown in Figure 7.3 by adding three 7474 D-flip-flip chips. Note that a clear function has been added and that the flip-flop presets are inactive since they are tied to +5V (labeled VCC).
Perform a simulation to verify the correct operation of the circuit. Note that in this case, the CLOCK signal is not a periodic signal; the CLOCK signal is a discrete signal occurring on a switch closure.
Assign pins to the inputs and outputs. Use the DIP switches for your inputs (0-3 for A, 8-11 for B, 7 for CLEAR, 15 for ADDSUB), one of the debounced pushbuttons for CLOCK and the red LEDs for outputs (RD0-4).
Download you program to the eSOC III board and test the operation of the circuit.
Photograph your final circuit for submission (online) or demonstrate your circuit to your professor (onsite or blended).
Why is the condition when both and are LOW considered illegal?
How do the values you measured for tPHL and tPLH compare with values specified in the 74LS112 data sheet? You may need to go online to find this value.
Why were the LEDs removed before making the propagation delay measurements?
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